Embodiments of the present invention relate to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device, and a method for manufacturing the same, in which a barrier metal layer is formed between a bit line contact plug and a bit line conductive layer when a bit line of a cell region is formed, such that interfacial resistance is reduced, a thickness of the bit line conductive layer is increased, conductivity is improved, and the height of the overall bit line is reduced, resulting in a reduction of parasitic capacitance.
A dynamic random access memory (DRAM) device includes a plurality of unit cells each having capacitors and transistors. The capacitor is used to temporarily store data, and the transistor is used to transfer data between a bit line and the capacitor in response to a control signal (word line). The data transfer occurs by using the semiconductor property that an electrical conductivity changes depending on the environment. The transistor has three regions, i.e., a gate, a source, and a drain. Electric charges move between the source and the drain according to a control signal input to the gate of the transistor. The movement of the electric charges between the source and the drain is achieved through a channel region. The semiconductor property is used in the channel.
In a typical method for manufacturing a transistor, a gate is formed in a semiconductor substrate, and a source and a drain are formed by doping impurities at both sides of the gate. In this case, a channel region of the transistor is defined between the source and the drain under the gate. The transistor having a horizontal channel region occupies a predetermined area of the semiconductor substrate. Therefore, the total number of unit cells per a wafer may depend on the size of the transistor.
If a unit cell size is reduce (or the size of each transistor is reduced), the number of semiconductor memory devices per wafer is increased, thereby improving productivity. Several methods for reducing the unit cell size have been proposed. One method is to replace a conventional planar gate having a horizontal channel region with a recess gate in which the recess is formed in a substrate and a channel region is formed along a curved surface of the recess by forming a gate in the recess. In addition, a buried gate has been studied, which can reduce a parasitic capacitance of a bit line by burying the entire gate within a recess.
In the conventional art, if a bit line conductive layer in a cell region is formed to be short (or shallow), resistance of the bit line conductive layer deteriorates. On the other hand, if the bit line conductive layer in the cell region is formed to be tall (or thick), parasitic capacitance between the bit line conductive layer and its neighboring storage node contact becomes severe, and the tall bit line conductive layer is prone to collapse. Furthermore, since a bit line of the cell region and a gate electrode of the peripheral circuit are simultaneously formed, a change in height of the bit line within the cell region affects the height of the gate electrode in the peripheral region. Accordingly, a shadowing effect occurs in a tilt implantation process of the peripheral region and thus makes it difficult or complicated to form a bit line and a peripheral gate at the same time in the cell region and in the peripheral region, respectively, in a subsequent process.